Silex — watch the same program race through a RISC vs a CISC pipeline

Write a program once in a tiny ISA-neutral assembly, lower it to up to three instruction sets, and run them on the same fair 5-stage pipeline (compiled to WebAssembly — the same C++ engine that passes the test suite). The ISA is the only variable; watch where CISC falls behind — that gap is why RISC won, measured to the cycle. Learn the theory →

examples

Registers t0, t1, … (virtual). Seed memory: .data ADDR v0 v1 …. Ops: const, add/sub/mul/and/or/xor/shl/shr, load tD,[tA+off], store [tA+off],tB, cmp + br.eq/ne/lt/ge/ltu/geu, jmp, ret.

compare
cycle —
Summary & live pipelines
Pipeline diagrams (Gantt: every µop × every cycle)
IF ID EX MEM WB load-use stall flag coupling (CISC) forwarding Each row is one micro-op; the five colored cells are its trip through the stages, on the cycle it issues. A gray cell is a stall; an orange ring is a flag-coupling hazard. The green dashed line is that ISA's finish — the leftmost one wins.